Distributed low voltage power supply system for front end electronics of the TRT detector in ATLAS experiment

We present a low voltage power supply system which has to deliver to the front end electronics of the ATLAS TRT detector [1] ca. 23 kW of electrical power over the distance of 55 -106 m (which adds another 24 kW). The system has to operate in magnetic field and under radiation environment of the LHC experimental cavern. The system has ~ 3000 individual channels which are all monitored and controlled (voltage and current measurement). The hardware solutions are described as well as the system control software

Report on Running Channels in iseg 32-Ch HV Power Supplies

We report a study and solution of the so-called "running channel" (RC) phenomenon observed in the iseg 32-channel HV power supplies for the ATLAS Liquid Argon Calorimetry

The ATLAS Level-1 Muon to Central Trigger Processor Interface

The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing (BC), the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six transverse momentum (pT) thresholds. This multiplicity value is then sent to the CTP, where it is used together with the input from the Calorimeter trigger to make the final Level-1 Accept (L1A) decision. In addition the MUCTPI provides summary information to the Level-2 trigger and to the data acquisition (DAQ) system for events selected at Level-1. This information is used to define the regions of interest (RoIs) that drive the Level-2 muontrigger processing. The MUCTPI system consists of a 9U VME chassis with a dedicated active backplane and 18 custom designed modules. The design of the modules is based on state-of-the-art FPGA devices and special attention was paid to low-latency in the data transmission and processing. We present the design and implementation of the final version of the MUCTPI. A partially populated MUCTPI system is already installed in the ATLAS experiment and is being used regularly for commissioning tests and combined cosmic ray data taking runs

Framework for Testing and Operation of the ATLAS Level-1 MUCTPI and CTP

The ATLAS Level-1 Muon-to-Central-Trigger-Processor Interface (MUCTPI) receives information on muon candidates from the muon trigger sectors and sends multiplicity values to the Central Trigger Processor (CTP). The CTP receives the multiplicity values from the MUCTPI and combines them with information from the calorimeter trigger and other triggers of the experiment and makes the final Level-1 decision. The MUCTPI and CTP are housed in two 9U VME64x crates and are made of nine different types of custom designed modules. This paper will present the framework which is used for debugging, commissioning and operation of all modules of the MUCTPI and CTP. Testing of the modules has been considered right from design. Most types of modules contain diagnostic memories at the input of the module which can be used to capture incoming data or to inject data into the module. Testing of the modules can be achieved by capturing data at input of a down-stream module, by reading out data from a monitoring buffer, or by reading out monitoring counters. A layered software framework using C++ has been developed for configuring and controlling all modules and for testing them independently or grouped into complete subsystems. The lowest level uses the ATLAS VME library and driver. At the next higher level, a compiler translates a description of the VME registers from XML to C++ code. This code together with existing code for some components, e.g. HPTDC, DELAY25, and JTAG, is combined to the lowlevel library of the module. A menu program provides access to all methods of the module low-level library. Generators create data for the test memories. Simulators calculate expected results. Generators, simulators and the low-level library are combined to a suite of test programs which cover the full functionality of the MUCTPI and CTP. The low-level library is also used by the control and monitoring programs which integrate the sub-systems into the ATLAS experiment control and monitoring framework

The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface

The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS Level-1 trigger receives data from the sector logic modules of the muon trigger at every bunch crossing and calculates the total multiplicity of muon candidates, which is then sent to the Central Trigger Processor where the final Level-1 decision is taken. The MUCTPI system consists of a 9U VME crate with a special backplane and 18 custom designed modules. We focus on the design and implementation of the octant module (MIOCT). Each of the 16 MIOCT modules processes the muon candidates from 13 sectors of one half-octant of the detector and forms the local muon candidate multiplicities for the trigger decision. It also resolves the overlaps between chambers in order to avoid double-counting of muon candidates that are detected in more than one sector. The handling of overlapping sectors is based on Look-Up-Tables (LUT) for maximum flexibility. The MIOCT also sends the information on the muon candidates over the custom backplane via the Readout Driver module to the Level-2 trigger and the DAQ systems when a Level-1 Accept is received. The design is based on state-of-the-art FPGA devices and special attention was paid to low-latency in the data transmission and processing

Hardware studies for the upgrade of the ATLAS Central Trigger Processor

The ATLAS Central Trigger Processor (CTP) is the final stage of the first level trigger system which reduces the collision rate of 40 MHz to a level-1 event rate of 75 kHz. The CTP makes the Level-1 trigger decision based on multiplicity values of various transverse-momentum thresholds as well as energy information received from the calorimeter and muon trigger sub-systems using programmable selection criteria. In order to improve the rejection rate for the first phase of the luminosity upgrade of the LHC to 3∙1034 cm-2 s-1 planned for 2015, one of the options being studied consists of adding a topological trigger processor, using Region-Of-Interest information from the calorimeter and potentially also the muon trigger. This will require an upgrade of the CTP in order to accommodate the additional trigger inputs. The current CTP system consists of a 9U VME64x crate with 11 custom designed modules where the functionality is largely implemented in FPGAs. The constraint for the upgrade study presented here was to reuse the existing hardware as much as possible. This is achieved by operating the backplane at twice the design frequency and required developing new FPGA firmware for several of the CTP modules. We present the design of the newly developed firmware for the input, monitoring and core modules of the CTP as well as results from initial tests of the upgraded system

A double-sided, shield-less stave prototype for the ATLAS upgrade strip tracker for the high luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools

The ATLAS level-1 Central Trigger

The ATLAS Level-1 Central Trigger consists of the Muon-to-Central-Trigger-Processor Interface (MUCTPI), the Central Trigger Processor (CTP), and the Timing, Trigger and Control (TTC) partitions of the sub-detectors. The MUCTPI connects the output of the muon trigger system to the CTP. At every bunch crossing it receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six pT thresholds. The CTP combines information from the calorimeter trigger and the MUCTPI and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). The MUCTPI and the CTP provide trigger summary information to the Level-2 trigger and to the data acquisition (DAQ) for every event selected at the Level-1. They further provide accumulated and, for the CTP, bunch-by-bunch counter data for monitoring of the trigger, detector and beam conditions. The TTC partitions send timing, trigger and control signals from the CTP to the sub-detectors and receive busy signals which can throttle the generation of L1As. The Local Trigger Processors (LTPs) normally receive the TTC signals from the CTP but can also generate them locally. The LTP interface (LTPIM) modules allow connecting of several LTPs for combined local running. The MUCTPI, the CTP and most of the TTC partitions of the ATLAS sub-detectors have been installed in the ATLAS experiment and are being used for commissioning tests with the trigger processors on the input and several sub-detectors as well as DAQ and Level-2 trigger on the output. Results of operating the Central Trigger in the experiment using trigger information from trigger processors connected to subdetectors observing cosmic rays will be shown

A double-sided silicon micro-strip super-module for the ATLAS inner detector upgrade in the high-luminosity LHC

The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail